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Low Noise, High Speed Amplifier for 16-Bit Systems AD8021
FEATURES
Low noise 2.1 nV/Hz input voltage noise 2.1 pA/Hz input current noise Custom compensation Constant bandwidth from G = -1 to G = -10 High speed 200 MHz (G = -1) 190 MHz (G = -10) Low power 34 mW or 6.7 mA typical for 5 V supply Output disable feature, 1.3 mA Low distortion -93 dBc second harmonic, fC = 1 MHz -108 dBc third harmonic, fC = 1 MHz DC precision 1 mV maximum input offset voltage 0.5 V/C input offset voltage drift Wide supply range, 5 V to 24 V Low price Small packaging Available in SOIC-8 and MSOP-8
CONNECTION DIAGRAM
LOGIC 1 REFERENCE -IN 2 +IN 3 -VS 4
AD8021
8 7 6 5
DISABLE +VS
VOUT CCOMP
01888-001
Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8)
The AD8021 allows the user to choose the gain bandwidth product that best suits the application. With a single capacitor, the user can compensate the AD8021 for the desired gain with little trade-off in bandwidth. The AD8021 is a well-behaved amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast overload recovery of 50 ns. The AD8021 is stable over temperature with low input offset voltage drift and input bias current drift, 0.5 V/C and 10 nA/C, respectively. The AD8021 is also capable of driving a 75 line with 3 V video signals. The AD8021 is both technically superior and priced considerably less than comparable amps drawing much higher quiescent current. The AD8021 is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations and can be used throughout a signal processing chain and in control loops. The AD8021 is available in both standard 8-lead SOIC and MSOP packages in the industrial temperature range of -40C to +85C.
APPLICATIONS
ADC preamps and drivers Instrumentation preamps Active filters Portable instrumentation Line receivers Precision instruments Ultrasound signal processing High gain circuits
24 21 18
CLOSED-LOOP GAIN (dB)
VOUT = 50mV p-p G = -10, RF = 1k, RG = 100, RIN = 100, CC = 0pF G = -5, RF = 1k, RG = 200, RIN = 66.5, CC = 1.5pF
GENERAL DESCRIPTION
The AD8021 is an exceptionally high performance, high speed voltage feedback amplifier that can be used in 16-bit resolution systems. It is designed to have both low voltage and low current noise (2.1 nV/Hz typical and 2.1 pA/Hz typical) while operating at the lowest quiescent supply current (7 mA @ 5 V) among today's high speed, low noise op amps. The AD8021 operates over a wide range of supply voltages from 2.25 V to 12 V, as well as from single 5 V supplies, making it ideal for high speed, low power instruments. An output disable pin allows further reduction of the quiescent supply current to 1.3 mA.
15 12 9 6 3 0 -3 -6 0.1M G = -2, RF = 499, RG = 249, RIN = 63.4, CC = 4pF G = -1, RF = 499, RG = 499, RIN = 56.2, CC = 7pF 1M 10M FREQUENCY (Hz) 100M 1G
Figure 2. Small Signal Frequency Response
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
01888-002
AD8021 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Connection Diagram ....................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 Maximum Power Dissipation ..................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Test Circuits................................................................................. 17 Applications..................................................................................... 19 Using the Disable Feature.......................................................... 20 Theory of Operation ...................................................................... 21 PCB Layout Considerations...................................................... 21 Driving 16-Bit ADCs ................................................................. 22 Differential Driver...................................................................... 22 Using the AD8021 in Active Filters ......................................... 23 Driving Capacitive Loads.......................................................... 23 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
5/06--Rev. E to Rev. F Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Figure 3.......................................................................... 7 Changes to Figure 60...................................................................... 19 Changes to Table 9.......................................................................... 23 3/05--Rev. D to Rev. E Updated Format..................................................................Universal Change to Figure 19 ....................................................................... 11 Change to Figure 25 ....................................................................... 12 Change to Table 7 and Table 8 ...................................................... 22 Change to Driving 16-Bit ADCs Section .................................... 22 10/03--Rev. C to Rev. D Updated Format..................................................................Universal 7/03--Rev. B to Rev. C Deleted All References to Evaluation Board...................Universal Replaced Figure 2 ..............................................................................5 Updated Outline Dimensions....................................................... 20 2/03--Rev. A to Rev. B Edits to Evaluation Board Applications....................................... 20 Edits to Figure 17 ........................................................................... 20 6/02--Rev. 0 to Rev. A Edits to Specifications .......................................................................2
Rev. F | Page 2 of 28
AD8021 SPECIFICATIONS
VS = 5 V, @ TA = 25C, RL = 1 k, gain = +2, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 2.5 V input step, G = +2 Min 355 160 150 110 95 120 250 380 AD8021AR/AD8021ARM Typ Max 490 205 185 150 120 150 300 420 23 50 Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 NTSC, RL = 150
-93 -108 -70 -80 2.1 2.1 0.03 0.04 0.4 0.5 7.5 10 0.1 86 10 1 -4.1 to +4.6 -98 -3.8 to +3.4 60 75 15/120 -40 45 50 1.75/1.90 70 2
dBc dBc dBc dBc nV/Hz pA/Hz % Degrees mV V/C A nA/C A dB M pF V dB V mA mA pF dB ns ns V A A
2.6
1.0 10.5 0.5
TMIN to TMAX +Input or -input
82
VCM = 4 V
-86 -3.5 to +3.2
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 2 V, 50% logic to 50% output VO = 0 V to 2 V, 50% logic to 50% output VDISABLE - VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V
Rev. F | Page 3 of 28
AD8021
Parameter Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio Conditions LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V Min AD8021AR/AD8021ARM Typ Max 30 33 5 7.0 1.3 -95 -95 12.0 7.7 1.6 Unit A A V mA mA dB dB
2.25 Output enabled Output disabled VCC = 4 V to 6 V, VEE = -5 V VCC = 5 V, VEE = -6 V to -4 V
-86 -86
VS = 12 V, @ TA = 25C, RL = 1 k, gain = +2, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 6 V input step, G = +2 Min 520 175 170 125 105 140 265 400 AD8021AR/AD8021ARM Typ Max 560 220 200 165 130 170 340 460 21 90 Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 NTSC, RL = 150
-95 -116 -71 -83 2.1 2.1 0.03 0.04 0.4 0.2 8 10 0.1 88 10 1 -11.1 to +11.6 -96
dBc dBc dBc dBc nV/Hz pA/Hz % Degrees mV V/C A nA/C A dB M pF V dB
2.6
1.0 11.3 0.5
TMIN to TMAX +Input or -input
84
VCM = 10 V
-86
Rev. F | Page 4 of 28
AD8021
Parameter OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio Conditions Min AD8021AR/AD8021ARM Typ Max -10.6 to +10.2 70 115 15/120 -40 45 50 1.80/1.95 70 2 30 33 2.25 Output enabled Output disabled VCC = 11 V to 13 V, VEE = -12 V VCC = 12 V, VEE = -13 V to -11 V 5 7.8 1.7 -96 -100 12.0 8.6 2.0 Unit V mA mA pF dB ns ns V A A A A V mA mA dB dB
-10.2 to +9.8
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 2 V, 50% logic to 50% output VO = 0 V to 2 V, 50% logic to 50% output VDISABLE - VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V
-86 -86
VS = 5 V, @ TA = 25C, RL = 1 k, gain = +2, unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 0 V to 2.5 V input step, G = +2 AD8021AR/AD8021ARM Min Typ Max 270 155 135 95 80 110 210 290 305 190 165 130 110 140 280 390 28 40 Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz
-84 -91 -68 -81 2.1 2.1
dBc dBc dBc dBc nV/Hz pA/Hz
2.6
Rev. F | Page 5 of 28
AD8021
Parameter DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio Conditions AD8021AR/AD8021ARM Min Typ Max 0.4 0.8 7.5 10 0.1 76 10 1 0.9 to 4.6 -98 1.10 to 3.60 30 50 10/120 -40 45 50 1.55/1.70 70 2 30 33 2.25 Output enabled Output disabled VCC = 4.5 V to 5.5 V, VEE = 0 V VCC = 5 V, VEE = -0.5 V to +0.5 V 5 6.7 1.2 -82 -84 12.0 7.5 1.5 1.0 10.3 0.5 Unit mV V/C A nA/C A dB M pF V dB V mA mA pF dB ns ns V A A A A V mA mA dB dB
TMIN to TMAX +Input or -input
72
1.5 V to 3.5 V
-84 1.25 to 3.38
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 1 V, 50% logic to 50% output VO = 0 V to 1 V, 50% logic to 50% output VDISABLE - VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V
-74 -76
Rev. F | Page 6 of 28
AD8021 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage Power Dissipation Input Voltage (Common Mode) Differential Input Voltage1 Differential Input Current Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec)
1
MAXIMUM POWER DISSIPATION
Rating 26.4 V Observed power derating curves VS 1 V 0.8 V 10 mA Observed power derating curves -65C to +125C -40C to +85C 300C
The maximum power that can be safely dissipated by the AD8021 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8021 is internally short-circuit protected, this can not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
The AD8021 inputs are protected by diodes. Current-limiting resistors are not used to preserve the low noise. If a differential input exceeds 0.8 V, the input current should be limited to 10 mA.
MAXIMUM POWER DISSIPATION (W)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
01888-004
0.01 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature 1
1
Specification is for device in free air: 8-lead SOIC: JA = 125C/W; 8-lead MSOP: JA = 145C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. F | Page 7 of 28
AD8021 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LOGIC 1 REFERENCE -IN 2 +IN 3 -VS 4
AD8021
8 7 6 5
DISABLE +VS
VOUT CCOMP
01888-003
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8
1
Mnemonic LOGIC REFERENCE -IN +IN -VS CCOMP VOUT +VS DISABLE
Description Reference for Pin 8 1 Voltage Level. Connect to logic low supply. Inverting Input. Noninverting Input. Negative Supply Voltage. Compensation Capacitor. Tie to -VS. (See the Applications section for value.) Output. Positive Supply Voltage. Disable, Active Low.
When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.
Rev. F | Page 8 of 28
AD8021 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 5 V, RL = 1 k, G = +2, RF = RG = 499 , RS = 49.9 , RO = 976 , RD = 53.6 , CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p, frequency = 1 MHz, unless otherwise noted.
24 21 18 G = +10, RF = 1k, RG = 110, CC = 0pF
9 G = +2 8 7 VS = 2.5V VS = 5V
CLOSED-LOOP GAIN (dB)
15 12 9 6 3 0 -3
G = +5, RF = 1k, RG = 249, CC = 2pF
6
GAIN (dB)
5 4 3 2 VS = 12V
G = +2, RF = RG = 499, CC = 7pF
G = +1, RF = 75, CC = 10pF
01888-005
1 0 -1 1M
VS = 2.5V
01888-008
-6 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
10M 100M FREQUENCY (Hz)
1G
Figure 5. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p, Noninverting (See Figure 48)
24 21 18 15 G = -10, RF = 1k, RG = 100, RIN = 100, CC = 0pF G = -5, RF = 1k, RG = 200, RIN = 66.5, CC = 1.5pF
Figure 8. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Noninverting (See Figure 48)
3 G = -1 2 1 0 VS = 2.5V VS = 5V
GAIN (dB)
GAIN (dB)
12 9 6 3 0
-1 -2 -3 -4 -5
VS = 12V
G = -2, RF = 499, RG = 249, RIN = 63.4, CC = 4pF G = -1, RF = 499, RG = 499, RIN = 56.2, CC = 7pF 1M 10M FREQUENCY (Hz) 100M 1G
01888-006
-3
-6 -7 1M
-6 0.1M
10M 100M FREQUENCY (Hz)
1G
Figure 6. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p Inverting (See Figure 48)
9 8 7 6 G = +2 CC = 5pF
Figure 9. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Inverting (See Figure 50)
9 G = +2 8 7 6 VOUT = 0.1V AND 50mV p-p
CC = 7pF
GAIN (dB)
GAIN (dB)
5 4 3 2 1 0 -1 0.1M 1M
CC = 9pF
5 4 3 2 VOUT = 1V p-p
01888-010
VOUT = 4V p-p
CC = 7pF
01888-007
1 0 -1 1M 10M 100M FREQUENCY (Hz) 1G
CC = 9pF 10M FREQUENCY (Hz) 100M 1G
Figure 7. Small Signal Frequency Response vs. Frequency and Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48)
Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting (See Figure 48)
Rev. F | Page 9 of 28
01888-009
VS = 2.5V
AD8021
10 9 8 7 G = +2
10 9 8 7
GAIN (dB)
G = +2 RF = RG
RF = 1k RF = 499
GAIN (dB)
6 5 4 3 2 1 0 0.1M 1M 10M FREQUENCY (Hz) 100M 1G RL = 100
01888-011
6 5 4 3 2 1 0 0.1M RF = 1k AND CF = 2.2pF 1M 10M FREQUENCY (Hz) 100M RF = 75
RF = 250 RF = 150
RL = 1k
1G
Figure 11. Large Signal Frequency Response vs. Frequency and Load, Noninverting (See Figure 49)
9 G = +2 8 7 6 +25C +85C
Figure 14. Small Signal Frequency Response vs. Frequency and RF, Noninverting, VOUT = 50 mV p-p (See Figure 48)
15 12 9 6 G = +2
GAIN (dB)
GAIN (dB)
5 4 3 2 1 0 -1 1M +25C +85C VOUT = 2V p-p
-40C
VOUT = 50mV p-p
3 0 -3 -6 -9
RS = 49.9
RS = 100
01888-012
-40C 10M 100M FREQUENCY (Hz) 1G
-12 -15 0.1M 1M 10M FREQUENCY (Hz)
100M
1G
Figure 12. Frequency Response vs. Frequency, Temperature, and VOUT, Noninverting (See Figure 48)
18 G = +2 15 12 20pF 50pF 30pF
Figure 15. Small Signal Frequency Response vs. Frequency and RS, Noninverting, VOUT = 50 mV p-p (See Figure 48)
100 90 80
OPEN-LOOP GAIN (dB)
9
70 60 50 40 30 20
GAIN (dB)
6 3 0 -3 -6 -9
135 90 45 0 -45 -90 100k 1M 10M FREQUENCY (Hz) 100M
0pF
01888-013
10 0 10k
-12 1M
100M 10M FREQUENCY (Hz)
1G
-135 1G
Figure 13. Small Signal Frequency Response vs. Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p (See Figure 49 and Figure 71)
Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 , RF = 1 k, RO = 976 , RD = 53.6 , CC = 0 pF (See Figure 50)
Rev. F | Page 10 of 28
01888-016
PHASE (Degrees)
10pF
180
01888-015
RS = 249
01888-014
AD8021
6.4 G = +2
-30 -20
6.2
VS = 2.5V
-40 -50
f1 f = 0.2MHz
f2
POUT 976 53.6 50
POUT (dBm)
01888-017
GAIN (dB)
6.0 VS = 5V
-60 -70 -80 -90
5.8
VS = 12V
5.6
-100 -110 -120 9.5 9.7 10.0 FREQUENCY (MHz) 10.3
01888-020
5.4 1M
10M FREQUENCY (Hz)
100M
10.5
Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p, RL = 150 , Noninverting (See Figure 49)
-20 -30
Figure 20. Intermodulation Distortion vs. Frequency
50
-50
SECOND
THIRD-ORDER INTERCEPT (dBm)
-40
45
DISTORTION (dBc)
-60 -70 -80 -90 -100 -110
01888-018
40
VS = 5V
35
RL = 100 RL = 1k
30
VS = 2.5V
25
01888-021
-120 -130 0.1M
THIRD 1M FREQUENCY (Hz) 10M
20M
20
0
5
10 FREQUENCY (MHz)
15
20
Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL
-30 -40 -50
Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage
-50 -60 -70 -80 -90 -100
DISTORTION (dBc)
-70 -80 -90 -100 -110 -120 THIRD SECOND
THIRD VS = 2.5V
DISTORTION (dBc)
-60 SECOND
SECOND RL = 100 THIRD SECOND RL = 1k
01888-022
VS = 5V SECOND 1M FREQUENCY (Hz)
01888-019
VS = 12V
-110 THIRD -120 1 2 3 4 VOUT (V p-p) 5 6
-130 100k
10M
20M
Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS
Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL
Rev. F | Page 11 of 28
AD8021
-50 -60 SECOND -70
3.5 3.4 -3.1 -3.2
POSITIVE OUTPUT
3.3 3.2 3.1 3.0 2.9 2.8 -3.3 -3.4 -3.5 -3.6 -3.7
fC = 5MHz
-80 THIRD -90 -100 -110 -120 SECOND
fC = 1MHz
01888-023
THIRD 1 2 3 4 VOUT (V p-p) 5 6
0
400
800 1200 LOAD ()
1600
-3.8 2000
Figure 23. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +2
-40 -50 -60 -70 THIRD -80 SECOND -90 -100 -110 THIRD
01888-024
Figure 26. DC Output Voltages vs. Load (See Figure 48)
120
DISTORTION (dBc)
SECOND
SHORT-CIRCUIT CURRENT (mA)
fC = 5MHz
100
VS = 12V
80
VS = 5.0V
60 VS = 2.5V 40
fC = 1MHz
20
01888-027
1
2
3 4 VOUT (V p-p)
5
6
0 -50
-30
-10
10
30
50
70
90
110
TEMPERATURE (C)
Figure 24. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +10
-70 RL = 1k RF = RG G = +2
Figure 27. Short-Circuit Current to Ground vs. Temperature
50
fC = 1MHz
G=2 40 30 20 RL = 1k, 150
-80
DISTORTION (dBc)
SECOND
-100 THIRD -110
01888-025
VOUT (mV)
-90
10
-10 -20 -30 -40 -50 0 40 80 120 TIME (ns) 160
01888-028
-120
0
200
400
600
800
1000
200
FEEDBACK RESISTANCE ()
Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF)
Figure 28. Small Signal Transient Response vs. RL, VO = 50 mV p-p, Noninverting (See Figure 49)
Rev. F | Page 12 of 28
01888-026
NEGATIVE OUTPUT
NEGATIVE OUTPUT VOLTAGE (V)
POSITIVE OUTPUT VOLTAGE (V)
DISTORTION (dBc)
AD8021
2.0 VO = 4V p-p G=2 RL = 1k 1.0
VOUT (V)
1.0 2.0 VO = 2V p-p G=2
RL = 150 -1.0
VOUT (V)
VS = 2.5V -1.0 VS = 5V
01888-029
-2.0 0 40 80 TIME (ns) 120 160
-2.0 0 40 80 120 TIME (ns) 160
200
200
Figure 29. Large Signal Transient Response vs. RL, Noninverting (See Figure 49)
5 4 3 2 1 VIN VO = 4V p-p G = -1
Figure 32. Large Signal Transient Response vs. VS (See Figure 48)
VIN = 3V G = +2 VIN = 1V/DIV VOUT = 2V/DIV
VOUT, RL = 1k
RL = 150
VOLTS
-1 -2 -3 -4 -5 0 50 100 150 TIME (ns) 200
01888-030
VOUT
VIN 0 100 200 300 TIME (ns) 400
250
500
Figure 30. Large Signal Transient Response, Inverting (See Figure 50)
Figure 33. Overdrive Recovery vs. RL (See Figure 49)
2.0
CL = 50pF G=2
VO = 4V p-p
G=2
OUTPUT SETTLING
1.0
CL = 10pF, 0pF
VOUT (V)
+0.01%
-0.01%
25ns
-1.0
01888-033
01888-032
-2.0 0 40 80 TIME (ns) 120 160
01888-031
VERT = 0.2mV/DIV
HOR = 5ns/DIV
200
Figure 31. Large Signal Transient Response vs. CL (See Figure 48)
Figure 34. 0.01% Settling Time, 2 V Step
Rev. F | Page 13 of 28
01888-034
AD8021
100 80 60 40 INPUT CURRENT NOISE (pA/Hz)
01888-035
100
SETTLING (V)
20 0 -20
PULSE WIDTH = 120ns
10
PULSE WIDTH = 300s -40 -60 -80 -100 0 5V 0V
t1
4 8 12 16 TIME (s) 20 24 28 32
1 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 35. Long-Term Settling, 0 V to 5 V, VS = 12 V, G = +13
50 40 30 20
Figure 38. Input Current Noise vs. Frequency
0.48
G = +1
0.44
VOLTAGE OFFSET (mV)
0.40
VOUT (mV)
10
0.36
-10 -20 -30 -40 -50 0 40 80 120 TIME (ns) 160
01888-036
0.32
0.28
01888-039
200
0.24 -50
-25
0
25
50
75
100
TEMPERATURE (C)
Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1 (See Figure 48)
100 8.4
Figure 39. VOS vs. Temperature
8.0
VOLTAGE NOISE (nV/ Hz)
INPUT BIAS CURRENT (A)
7.6
10
7.2
6.8
2.1nV/Hz
01888-037
6.4
01888-040
1 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
6.0 -50
-25
0
25
50
75
100
TEMPERATURE (C)
Figure 37. Input Voltage Noise vs. Frequency
Figure 40. Input Bias Current vs. Temperature
Rev. F | Page 14 of 28
01888-038
AD8021
-20 -30
0 -10 -20
DISABLED ISOLATION (dB)
-40 -50
-30 -40 -50 -60 -70 -80
CMRR (dB)
-60 -70 -80 -90
-100
01888-041
-110 -120 10k 100k 1M FREQUENCY (Hz) 10M
-90 -100 0.1M 1M 10M FREQUENCY (Hz) 100M 1G
100M
Figure 41. CMRR vs. Frequency (See Figure 51)
Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54)
300 100 30
300k 100k 30k
OUTPUT IMPEDANCE ()
10 3 1 0.3 0.1 0.03
01888-042
OUTPUT IMPEDANCE ()
10k 3k 1k 300 100 30 10 3 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G
01888-045
0.01 0.003 10k 100k 10M 1M FREQUENCY (Hz) 100M 1G
Figure 42. Output Impedance vs. Frequency, Chip Enabled (See Figure 52)
DISABLE
Figure 45. Output Impedance vs. Frequency, Chip Disabled (See Figure 55)
0 -10 -20 -30 -PSRR
4V 2V
2V
VOUTPUT
PSRR (dB)
-40 -50 -60 -70 -80 VS = 5V
01888-046
VS = 2.5V
+PSRR VS = 12V
tEN = 45ns
1V
tDIS = 50ns
01888-043
-90 -100 10k 100k 1M 10M FREQUENCY (Hz) 100M
0
100
200
300 TIME (ns)
400
500
500M
Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53)
Figure 46. PSRR vs. Frequency and Supply Voltage (See Figure 56 and Figure 57)
Rev. F | Page 15 of 28
01888-044
AD8021
8.5
8.0
SUPPLY CURRENT (mA)
7.5
7.0
6.5
6.0
01888-047
5.5 -50
-25
0
25
50
75
100
TEMPERATURE (C)
Figure 47. Quiescent Supply Current vs. Temperature
Rev. F | Page 16 of 28
AD8021 TEST CIRCUITS
50 CABLE 50 5 RIN 49.9 CC -VS RG RF
01888-048
RS
+VS RO 50 CABLE
AD8021
+VS 100 CC 7pF -VS
HP8753D NETWORK ANALYZER
RD
5
50
Figure 48. Noninverting Gain
FET PROBE
Figure 52. Output Impedance, Chip Enabled
AD8021
49.9 +VS 1 LOGIC REF 8 DISABLE 5 CC -VS
01888-049
50 CABLE 50 RIN 49.9
+VS RS
5 CC RF CF
1.0V CL RL 4V
49.9
976 53.6
-VS RG
49.9
7pF
01888-053
499
499
Figure 49. Noninverting Gain and FET Probe
+VS RO 49.9 5 RD 50 CABLE 50 RIN 49.9 RG -VS CC RF
01888-050
Figure 53. Enable/Disable
HP8753D
50 CABLE
NETWORK ANALYZER 50 50 50 CABLE +VS 49.9 49.9 1 8
AD8021
LOGIC REF DISABLE
FET PROBE 1k
Figure 50. Inverting Gain
5
HP8753D NETWORK ANALYZER 50 50 499
-VS 499
CC 7pF
01888-054
Figure 54. Input-to-Output Isolation, Chip Disabled
49.9
AD8021
499 499 CC -VS 55.6 499 7pF 499 +VS 5
AD8021
1 100 8 +VS 5 CC 7pF 50
HP8753D NETWORK ANALYZER
01888-051
-VS
Figure 51. CMRR
Figure 55. Output Impedance, Chip Disabled
Rev. F | Page 17 of 28
01888-055
01888-052
CF
RG 499
RF 499
AD8021
BIAS BNC 50 +VS HP8753D NETWORK ANALYZER 50
BIAS BNC 50 -VS
HP8753D NETWORK ANALYZER 50
50 CABLE 49.9, 5W +VS 976 249 5 CC 7pF
01888-056
50 CABLE +VS 249 976 5 CC 7pF 53.6
53.6
-VS 49.9 5W
-VS 499
499
499
Figure 56. Positive PSRR
Figure 57. Negative PSRR
Rev. F | Page 18 of 28
01888-057
499
AD8021 APPLICATIONS
The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, CINTERNAL, using dominant pole compensation. To a first-order approximation, voltage feedback op amps have a fixed gain bandwidth product. For example, if its -3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain of G = +10, its bandwidth is only about 20 MHz. The AD8021 is a voltage feedback op amp with a minimal CINTERNAL of about 1.5 pF. By adding an external compensation capacitor, CC, the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. Unlike the typical op amp with fixed compensation, the AD8021 allows the user to: * Maximize the amplifier bandwidth for closed-loop gains between 1 and 10, avoiding the usual loss of bandwidth and slew rate. Optimize the trade-off between bandwidth and phase margin for a particular application. Match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in Figure 65).
110 100 90 86 80 70 60 50 40 30 20 10 0 -10 1k 10k 100k
01888-058
degraded to about 20 MHz and the phase margin increases to 90 (Arrow B). However, by reducing CC to 0 pF, the bandwidth and phase margin return to about 200 MHz and 60 (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of CC.
10 COMPENSATION CAPACITANCE (pF) 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 NOISE GAIN (V/V) 8 9 10 11
01888-059
* *
Figure 59. Suggested Compensation Capacitance vs. Gain for Maintaining 1 dB Peaking
180 135 90 CC = 0pF CC = 10pF (B) (A) (C) 45
PHASE (Degrees)
OPEN-LOOP GAIN (dB)
0
Table 6 and Figure 59 provide recommended values of compensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. Note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. As shown in Figure 60, the noise gain, GN, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, Noninverting GN = RF/RG + 1 Inverting GN = RF/RG + 1
RS 3 RG 249 + 6 5 -VS CCOMP G = GN = +5 NONINVERTING RG 249 RF 1k 3 + -VS CCOMP INVERTING 2 - RF 1k
(C)
(B) (A) 10M 100M 1M FREQUENCY (Hz) 1G 10G
1
AD8021
2 -
AD8021
5
6
Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response
Figure 58 is the AD8021 gain and phase plot that has been simplified for instructional purposes. Arrow A in Figure 58 shows a bandwidth of about 200 MHz and a phase margin at about 60 when the desired closed-loop gain is G = +1 and the value chosen for the external compensation capacitor is CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at 10 pF, then (as expected for a typical op amp) the bandwidth is
G = -4 GN = +5
01888-060
Figure 60. The Noise Gain of Both is 5
Rev. F | Page 19 of 28
AD8021
CF = CL = 0, RL = 1 k, RIN = 49.9 (see Figure 49). Table 6. Recommended Component Values
Noise Gain (Noninverting Gain) 1 2 5 10 20 100 -3 dB SS BW (MHz) 490 205 185 150 42 6 Output Noise (AD8021 Only) (nV/Hz) 2.1 4.3 10.7 21.2 42.2 211.1 Output Noise (AD8021 with Resistors) (nV/Hz) 2.8 8.2 15.5 27.9 52.7 264.1
RS () 75 49.9 49.9 49.9 49.9 49.9
RF () 75 499 1k 1k 1k 1k
RG () NA 499 249 110 52.3 10
CCOMP (pF) 10 7 2 0 0 0
Slew Rate (V/s) 120 150 300 420 200 34
With the AD8021, a variety of trade-offs can be made to finetune its dynamic performance. Sometimes more bandwidth or slew rate is needed at a particular gain. Reducing the compensation capacitance, as illustrated in Figure 7, increases the bandwidth and peaking due to a decrease in phase margin. On the other hand, if more stability is needed, increasing the compensation capacitor decreases the bandwidth while increasing the phase margin. As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, as well as the PC board) has a significant effect. The feedback resistance, together with the input capacitance, can contribute to a loss of phase margin, thereby affecting the high frequency response, as shown in Figure 14. A capacitor (CF) in parallel with the feedback resistor can compensate for this phase loss.
Additionally, any resistance in series with the source creates a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance), the effect of which is shown in Figure 15. It must also be noted that increasing resistor values increases the overall noise of the amplifier and that reducing the feedback resistor value increases the load on the output stage, thus increasing distortion (see Figure 22).
USING THE DISABLE FEATURE
When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of Pin 1, the part is disabled. See Table 1 for exact disable and enable voltage levels. If the disable feature is not used, Pin 8 can be tied to VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.
Rev. F | Page 20 of 28
AD8021 THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog Devices proprietary High Voltage eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 3 GHz region. The transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. It also reduces nonlinear capacitance (a source of distortion) and allows a higher transistor, fT, for a given quiescent current. The supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. As shown in Figure 61, the AD8021 input stage consists of an NPN differential pair in which each transistor operates at a 0.8 mA collector current. This allows the input devices a high transconductance; thus, the AD8021 has a low input noise of 2.1 nV/Hz @ 50 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. The folded cascode and current mirror provide a differential-to-single-ended conversion of signal current. This current then drives the high impedance node (Pin 5), where the CC external capacitor is connected. The output stage preserves this high impedance with a current gain of 5000, so that the AD8021 can maintain a high open-loop gain even when driving heavy loads. Two internal diode clamps across the inputs (Pin 2 and Pin 3) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset voltage and input bias current.
+VS
PCB LAYOUT CONSIDERATIONS
As with all high speed op amps, achieving optimum performance from the AD8021 requires careful attention to PC board layout. Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. Otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. Use of a multilayer printed circuit board, with an internal ground plane, reduces ground noise and enables a compact component arrangement. Due to the relatively high impedance of Pin 5 and low values of the compensation capacitor, a guard ring is recommended. The guard ring is simply a PC trace that encircles Pin 5 and is connected to the output, Pin 6, which is at the same potential as Pin 5. This serves two functions. It shields Pin 5 from any local circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. An example of a guard ring layout is shown in Figure 62. Also shown in Figure 62, the compensation capacitor is located immediately adjacent to the edge of the AD8021 package, spanning Pin 4 and Pin 5. This capacitor must be a high quality surfacemount COG or NPO ceramic. The use of leaded capacitors is not recommended. The high frequency bypass capacitor(s) should be located immediately adjacent to the supplies, Pin 4 and Pin 7. To achieve the shortest possible lead length at the inverting input, the feedback resistor RF is located beneath the board and spans the distance from the output, Pin 6, to inverting input Pin 2. The return node of Resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor connected to Pin 4.
(TOP VIEW) DISABLE BYPASS CAPACITOR
OUTPUT +IN
CINTERNAL 1.5pF -IN -VS CCOMP
01888-061
LOGIC REFERENCE
1 2 3 4
8 +VS 7 6 5
-IN +IN -VS METAL BYPASS CAPACITOR
VOUT GROUND PLANE CCOMP
CC
Figure 61. Simplified Schematic
COMPENSATION CAPACITOR GROUND PLANE
01888-062
Figure 62. Recommended Location of Critical Components and Guard Ring
Rev. F | Page 21 of 28
AD8021
DRIVING 16-BIT ADCs
Low noise and adjustable compensation make the AD8021 especially suitable as a buffer/driver for high resolution ADCs. As seen in Figure 19, the harmonic distortion is better than 90 dBc at frequencies between 100 kHz and 1 MHz. This is an advantage for complex waveforms that contain high frequency information, because the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample. This advantage is particularly apparent when using 16-bit high resolution ADCs with high sampling rates. Figure 63 shows a typical ADC driver configuration. The AD8021 is in an inverting gain of -7.5, fC is 65 kHz, and its output voltage is 10 V p-p. The results are listed in Table 7.
+12V 3 590 2 +5V 6 5 IN HI
Table 8. Summary of ADC Driver Performance (fC = 100 kHz, VOUT = 20 V p-p)
Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR Measurement -92.6 -86.4 -84.4 +5.4 Unit dBc dBc dBc dBc
DIFFERENTIAL DRIVER
The AD8021 is uniquely suited as a low noise differential driver for many ADCs, balanced lines, and other applications requiring differential drive. If pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter is higher than that of the follower section, resulting in an imbalance in the frequency response (see Figure 66). A better solution takes advantage of the external compensation feature of the AD8021. By reducing the CCOMP value of the inverter, its bandwidth can be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. The inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion. Figure 65 illustrates an inverter-follower driver circuit operating at a gain of 2, using individually compensated AD8021s. The values of feedback and load resistors were selected to provide a total load of less than 1 k, and the equivalent resistances seen at each op amp's inputs were matched to minimize offset voltage and drift. Figure 67 is a plot of the resulting ac responses of driver halves.
VIN 49.9 249 3+ G = +2 6 5
+ AD8021 -
CC 10pF
RG 200 50
-12V
RF 1.5k
570kSPS
Figure 63. Inverting ADC Driver, Gain = -7.5, fC = 65 kHz
Table 7. Summary of ADC Driver Performance (fC = 65 kHz, VOUT = 10 V p-p)
Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR Measurement -101.3 -109.5 -100.0 +100.3 Unit dBc dBc dBc dBc
01888-063
56pF
IN HI
16 BITS
AD7665
AD8021
2 - 7pF 499
-VS 499
332
664
+12V 50 3 + 50 +5V 6 5 CC RF 750 IN HI
Figure 65. Differential Amplifier
50
AD8021
2 - -12V
AD7665
570kSPS ADC
RG 82.5
OPTIONAL CF
Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
Rev. F | Page 22 of 28
01888-064
IN LO
16 BITS
01888-065
Figure 64 shows another ADC driver connection. The circuit was tested with a noninverting gain of 10.1 and an output voltage of approximately 20 V p-p for optimum resolution and noise performance. No filtering was used. An FFT was performed using Analog Devices evaluation software for the AD7665 16-bit converter. The results are listed in Table 8.
VOUT1 1k
232
3+
G = -2 6 5 1k VOUT2
AD8021
2 - 5pF
-VS
AD8021
12 9 6 3
GAIN (dB)
VIN R1 R2 C2 3 2 CC -VS RG
01888-068
C1 +VS
AD8021
6 5 VOUT
0 -3 -6 -9
G = -2 G = +2
RF
Figure 68. Schematic of a Second-Order, Low-Pass Active Filter
01888-066
-12 -15 -18 100k 1M 10M FREQUENCY (Hz) 100M
Table 9. Typical Component Values for Second-Order, LowPass Active Filter of Figure 68
Gain 2 5 R1 () 71.5 44.2
50 40 30
1G
Figure 66. AC Response of Two Identically Compensated High Speed Op Amps Configured for a Gain of +2 and a Gain of -2
12 9 6 3 G = 2
R2 () 215 365
RF () 499 365
RG () 499 90.9
C1 (nF) 10 10
C2 (nF) 10 10
CC (pF) 7 2
20
G=5
GAIN (dB)
0 -3
GAIN (dB)
10 0 -10 -20 -30 G=2
-6
-9 -12 -15 -18 100k 1M 10M FREQUENCY (Hz) 100M
01888-067
-40 -50 1k 10k 100k FREQUENCY (Hz) 1M
1G
10M
Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps (Figure 66) Configured for a Gain of +2 and a Gain of -2, (Note the Close Gain Match)
Figure 69. Frequency Response of the Filter Circuit of Figure 68 for Two Different Gains
USING THE AD8021 IN ACTIVE FILTERS
The low noise and high gain bandwidth of the AD8021 make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the op amp's finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. Good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. Figure 68 shows the schematic of a 2-pole, low-pass active filter and lists typical component values for filters having a Besseltype response with a gain of 2 and a gain of 5. Figure 69 is a network analyzer plot of this filter's performance.
DRIVING CAPACITIVE LOADS
When the AD8021 drives a capacitive load, the high frequency response can show excessive peaking before it rolls off. Two techniques can be used to improve stability at high frequency and reduce peaking. The first technique is to increase the compensation capacitor, CC, which reduces the peaking while maintaining gain flatness at low frequencies. The second technique is to add a resistor, RSNUB, in series between the output pin of the AD8021 and the capacitive load, CL. Figure 70 shows the response of the AD8021 when both CC and RSNUBB are used to reduce peaking. For a given CL, Figure 71 can be used to determine the value of RSNUB that maintains 2 dB of peaking in the frequency response. Note, however, that using RSNUB attenuates the low frequency output by a factor of RLOAD/(RSNUBB + RLOAD).
B B
Rev. F | Page 23 of 28
01888-069
AD8021
18 16 14 12
GAIN (dB)
+VS 49.9 49.9 -VS 499 CC 499
FET PROBE 5 RSNUB 6 33pF RL 1k
20 CC = 7pF; RSNUB = 0 CC = 8pF; RSNUB = 0
R SNUB ()
01888-070
18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CAPACITIVE LOAD (pF)
B
10 8 6 4 2 0 0.1
1.0
10 FREQUENCY (MHz)
100
1000
40
45
50
Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF
Figure 71. Relationship of RSNUB vs. CL for 2 dB Peaking at a Gain of +2
Rev. F | Page 24 of 28
01888-071
CC = 8pF; RSNUB = 17.4
AD8021 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 72. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
3.20 3.00 2.80
3.20 3.00 2.80 PIN 1
8
5
1
5.15 4.90 4.65
4
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 73. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8021AR AD8021AR-REEL AD8021AR-REEL7 AD8021ARZ 1 AD8021ARZ-REEL1 AD8021ARZ-REEL71 AD8021ARM AD8021ARM-REEL AD8021ARM-REEL7 AD8021ARMZ1 AD8021ARMZ-REEL1 AD8021ARMZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP
Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8
Branding
HNA HNA HNA HNA# HNA# HNA#
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. F | Page 25 of 28
AD8021 NOTES
Rev. F | Page 26 of 28
AD8021 NOTES
Rev. F | Page 27 of 28
AD8021 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01888-0-5/06(F)
Rev. F | Page 28 of 28

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